An IEEE standard known as IEEE ISTO5001, or the Nexus debug standard, is an established real-time debug standard that supports real-time debug message generation. Debugging is a commonly used term that generally refers to testing of software or electronic circuitry to identify defects or “bugs” for the purpose of identification and reduction of the errors. The Nexus debug standard specifies a mechanism for identifying to an external trace reconstruction tool a predetermined operating condition within the system. Debugging processes are also used in the development of code for a data processing system.
Some data processing systems use multiple processors with closely coupled cache memories. A cache memory stores a subset of duplicative information that is stored in the system memory. Using a cache in the system may reduce the number of occurrences that a processor must communicate with the system memory via a system interconnect. However, the presence of various caches (or other memory devices) in a system can readily permit a data operand which has the same identifier or address to be present at various locations in the system. When the data operand is modified in one part of the system, an opportunity exists that an old version of the data operand will be stored or used. Memory coherency refers to the need of each processor in a multiple master data processing system to have access to the most recently modified data corresponding to a particular address in the memory system. The presence of differing data values for a same address value in a data processing system may lead to system errors.
To maintain memory coherency, reads and writes of information to the system memory are monitored or “snooped”. When either a memory read or a memory write of data at an address is detected, this address of the transaction is used as a snoop address. A snoop request is initiated and directed to all caches in the system such that snoop lookups can be performed to search for any address in the caches that match the snoop address. A snoop hit occurs for every match, and any needed corrective action is taken to maintain coherency of the data at the address in the cache where the snoop hit occurs.
For a processor cache with a single set of tags, arbitration is needed between processor requests to search for addresses in its own cache (such as for performing a load or store instruction whose corresponding access address may be contained in the cache) and snoop requests to perform snoop lookups in the cache. In one arbitration solution used today, any pending snoop request blocks the processor from accessing its cache for one or more cycles. If snoop lookups occur frequently, then processor performance may be negatively impacted.
The debugging of a multiple core data processing system is a difficult and time consuming operation. Numerous aspects of the internal operation remain hidden from the debugger. The amount of parallel processing in such systems, along with the relatively non-predictable behavior of multi-core systems make debugging difficult, particularly with respect to shared memory and other shared resources. Arbitration, collisions for shared resources, cache conflicts and coherency transactions cause system behavior to appear non-deterministic to a user. Therefore assistance in debugging system scenarios that involve cache coherency operations is needed.
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